Innovation, not scaling key to future ICs, says IBM exec

Dave Bursky
EE Times
(02/28/2006 1:21 PM EST)

MONTEREY, Calif. — When Dr. Bernard Meyerson, vice president of strategic alliances and chief technical officer of IBM Corp. speaks, the industry listens.

In a keynote at Global Press Summit in Monterey earlier this week, Meyerson reiterated his view that innovation, not scaling will have to drive next-generation IC development.

Meyerson pointed out that atoms do not scale as the industry pushes for smaller features and thinner oxides. Instead, he called for device, circuit, and architectural innovations to push up system performance. The industry can no longer just increase clock frequency to increase performance, since higher frequencies and higher integration levels increase processor power consumption, pushing today's devices to their upper limits in air-cooled systems.

Tracing semiconductor development since the late 1960s, Meyerson described two inflection points. In the first, designers in the 1960's and 1970's pushed bipolar technology from chips with just a few transistors to circuits with tens of thousands of gates, until the chips became too power-hungry to integrate more logic.

As bipolar was reaching its limit, a new technology, CMOS, was in its infancy and promised to increase performance and density but at much lower power levels than bipolar. Since the 1970s, designers have been driving CMOS to higher levels of gate counts and performance, such that current CMOS chips are just as power-hungry as earlier bipolar circuits.

Meyerson points out the industry is now at a second inflection point, but lacks a new technology to replace CMOS near-term. Promising technologies such as carbon nanotubes remain 10 to 15 years away.

For the next decade, Meyerson believes technologies such as strained silicon and silicon-on-insulator, as well as new device structures such as dual-gate and finFET transistors, will enable chip designers to create next-generation circuits with 45- nanometer 32-nanometer, and smaller feature dimensions using established CMOS logic techniques.

But it is not just a matter of applying these structures to achieve increased levels of performance. Using the company's BlueGene high performance supercomputing systems as an example, Meyerson explained that even though the system only uses 800 MHz processors, it delivers world-class performance through architectural innovation. This includes deploying many parallel processors and a highly-efficient communications infrastructure allowing many processors to rapidly transfer data so idling time is minimized.

Referring to the optimization of all aspects of the system as holistic design, Meyerson explains that IBM was able to achieve industry-leading performance without requiring maximum chip performance and still deliver systems that were one-twentieth the size and one-twenty-eighth the power of the closest competitor.

Meyerson believes the same concept can be applied at the chip level, first through virtualization by allowing one processor to run multiple program threads so that it never has an idle state. The second step would be to integrate multiple processors on the same chip as other processor vendors have already started to do.

One multiprocessor solution is the Cell processor, on which IBM teamed with Sony Corp. and Toshiba Corp. to develop. Sony will use the Cell chip in its forthcoming Playstation 3 game console.

Meyerson concluded the presentation by stating it would likely cost more to innovate as feature sizes shrink. To spread the cost, he suggested companies form partnerships, as few will be able to single-handedly finance next-generation fabs.

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