Brute scaling not the answer, IEDM hears

By David Lammers and Nicolas Mokhoff
EE Times
(12/12/2005 10:00 AM EST)

Washington — With CMOS power limitations in force, technologists are looking to a broader array of technologies to extend system performance in a new era that is being described as "More than Moore."

During the three days of the International Electron Devices Meeting here last week, industry leaders urged the 1,700 IEDM participants to look beyond brute transistor scaling to new applications and user interfaces. In recent years, IEDM has broadened its own focus, staging as many as eight parallel sessions to accommodate traditional presentations on high-k dielectrics and the like along with future-looking sessions on emerging technologies such as organic semiconductors and carbon nanowires.

In a stirring keynote address, Benedetto Vigna, a director at STMicroelectronics, said that "after the 'nomadic era' in which we are currently living, wireless sensor networks, domestic robots, smart pills and lab-on-chip applications are coming, aided by a new generation of low-power microelectromechanical systems."

Electronics engineers must de-emphasize megahertz and realize there can be "serious energy costs" from brute Moore's Law scaling, said Stanford University professor Mark Horowitz. Instead, engineers must hone their ability to design parallel-processing systems that stay within the power limits of their applications.

Meanwhile, IBM Corp. technologists introduced a new performance-enhancing technique: combining different silicon crystal orientations on bulk silicon wafers.

At IEDM two years ago, IBM researcher Min Yang described a somewhat more complex process of putting both 110-oriented silicon and the conventional 100 crystal lattice on silicon-on-insulator (SOI) wafers. IBM called that approach HOT, or hybrid orientation technology, drawing upon the faster performance of PFETs in 110 silicon.

Last week, IBM took the HOT approach to bulk (non-SOI) silicon wafers, using a direct silicon bond technique. This DSB approach uses solid-phase epitaxy to convert 110 silicon to 100 silicon, said researcher Haizhou Yin. Yin called the approach "cost-effective," though it still requires bonding a handle wafer with a 100 substrate to a 110-oriented layer of silicon. A PFET placed on the 110 silicon showed a 35 percent current enhancement over conventional PFETs made on 100 bulk silicon, he said. Combined with the NFET on 100-oriented silicon, the net result was a 20 percent faster ring oscillator — nearly equivalent to one generation of device scaling, said Yin. The solid-phase epitaxy conversion resulted in nearly defect-free 100 silicon, he said.

The approach is being looked upon favorably by Intel Corp., which has avoided SOI technology. Kaizad Mistry, manager of Intel's 45-nm node, said he believes IBM's DSB scheme has merit. "Mobility enhancement through strain will continue for a while," Mistry told EE Times. "We believe the industry can extend that over three generations. Then the alternate crystal orientations and perhaps new planar structures will come in."

High-k doubts for 45 nm
The biggest mystery hanging over the industry is whether high-k will be ready at the 45-nm node, now in the final stages of development at Intel and elsewhere.

Nick Kepler, vice president of logic technology development at Advanced Micro Devices Inc. (Sunnyvale, Calif.), said AMD makes six to eight changes in its process recipe over the lifetime of a process generation. While high-k is unlikely to be used in the first 45-nm process, it could be ready at some later point, added in much the same way AMD retrofitted its 90-nm process to accept the embedded silicon germanium stressors at the PMOS.

Bob Doering, a technology strategist at Texas Instruments Inc. and a U.S. representative to the International Technology Roadmap for Semiconductors (ITRS), said the industry is "in a big crunch. We've skipped a couple of generations without really scaling the gate oxide, and we will definitely be needing it in the 2008 time frame."

The 2005 edition of the ITRS, slated to roll out this week at a meeting in Seoul, South Korea, "will say that high-k has slipped out again," Doering said.

One possibility is that some chip manufacturers may introduce a fully silicided (FUSI) form of a metal gate electrode at the 45-nm node, using a non-high-k gate oxide. Bringing in FUSI gates alone would reduce poly depletion effects.

"There is a fighting chance that what the industry calls the 45-nm node will have a metal gate in the form of FUSI. It is coming along nicely," Doering said.

However, doped FUSI gates thus far do not provide the good work function — separating the carriers to the edge of valence and conduction bands — needed for high-performance silicon.

Mistry said Intel's work on FUSI metal gates with a silicon dioxide, presented at IEDM, showed that the work function for the PMOS transistor "is not good enough. We would have to improve on FUSI to make it a competitive approach."

IBM, for its part, does not have FUSI on its road map, according to Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y.

"IBM has done a lot of work on FUSI, but it is not on our list of options," he said in an interview.

Stretching strain
In lieu of FUSI, some companies are emphasizing strain engineering. Strained silicon, first introduced by Intel at the 90-nm node, has been adopted by many other chip makers at 65 nm. The results have been startling, said Mark Pinto, chief technology officer at Applied Materials Inc., with PFET performance boosted by nearly 100 percent from the unstrained 130-nm node to the fully strained 65-nm node. The electron carriers in the NFET responded to tensile strain with a 50 percent boost in mobility.

"Strain is the best of what we've got in our toolbox right now," Pinto said.

At IEDM, technologists from a Toshiba-Sony research group presented data showing that strain techniques may continue to work their magic at 45 nm. The Sony-Toshiba team concluded that stress techniques "are scalable for future technologies," said A. Oishi, an engineer working at Toshiba Corp.'s system-on-chip R&D center in Yokohama, Japan.

Yale University professor T.P. Ma noted, however, that overall results indicate "diminishing returns" at the 45-nm node. "Silicon is already under a very large strain — the lattice is stretched [on the NFET] or compressed [on the PFET] by about 1 percent," Ma said.

In one sense, shrinking the device is a friend of strained silicon: As the channel length shrinks, the smaller amount of silicon is easier to bring under strain. But scaling also means there is less space to deposit the germanium atoms, which exert a compressive stress on the silicon lattice in the PFET. The nitride capping layers also take up space.

As MIT professor Gene Fitzgerald explained, the higher strain can cause "dislocation issues that some process engineers haven't had to deal with in 30 years."

Can strained silicon and the hybrid orientation technology be combined? IBM data shows that the hybrid orientation improvement and strain techniques indeed complement each other, even at high levels of strain, said Wilfried Haensch, senior manager of device and design integration at IBM. Meikei Ieong, manager of exploratory devices at the company's T.J. Watson Research Center, agreed, saying that IBM is considering whether to bring in the hybrid orientation technology at the 45-nm node.

"There is a small benefit to strained silicon as we scale," Ieong said. But on the flip side, "there is a smaller space between the transistors" in which to deposit SiGe in the PFET source and drain regions."

"As we shrink, scaling increases the strain by 1.3 or 1.4 times," said Scott Thompson, a University of Florida at Gainesville professor who helped develop Intel's strained-silicon techniques when he managed the company's 90-nm process technology development in Hillsboro, Ore. "There was a major boost in performance as Intel went from 90 nm to 65 nm, and I believe there will be the same kind of boost as companies go from 65 nm to 45 nm."

Better beta ratio
Strain has been so spectacularly successful that it is altering the beta ratio: the difference in size between the inherently weaker PMOS and the traditionally stronger NMOS transistors.

The ratio between N and P transistors was about 2.2 to 2.4 before strain techniques were introduced. At the 65-nm node, Intel's beta ratio is in the 1.8 to 2.0 range, and that may improve further, Mistry said, attaining 1.5 to 1.6.

That means the PMOS transistors would need only be half again as large as the NMOS transistors to achieve a balanced performance.

Intel fellow Paolo Gargini said the better beta ratio will help the design community. Circuit designers pioneered domino circuits to come up with faster ICs, despite the imbalanced N and P drive currents. They are likely to devise new techniques to take advantage of the much faster PFETs, Gargini said.

"Before strain, if circuit designers wanted highly symmetric performance, they had to make the PFET much bigger," he said. "Now, the improved beta ratio allows designers options that they didn't have before strain."

Partners unite
Elsewhere at IEDM, Hisatsune Watanabe, president of the semiconductor research consortium Selected Leading Edge Technologies Inc., announced that Selete will continue beyond April 2006, thanks to additional backing from the Japanese government and the continued support of the four largest Japanese integrated device manufacturers — Fujitsu, NEC, Renesas and Toshiba.

Selete is one of many cooperative efforts under way in chip manufacturing. The East Fishkill alliance among IBM, AMD, Sony and Toshiba, the Crolles alliance in France and Toshiba's decision to share its process technology development effort with NEC in Yokohama are other examples.

"Competitors are engaging in 'coopetition,' because the R&D costs are growing at a rate that is simply unsustainable," said IBM vice president Bernie Meyerson, speaking at an IEDM panel.

Gargini agreed. "We know what we have to do," he said. "It's a matter of executing to keep us on the projected road map for faster, cheaper, smaller chips."

About AmberWave Systems
Founded in 1998, AmberWave Systems has become a leader in the research, development and licensing of advanced technologies for semiconductor manufacturing. By funding and guiding university research, AmberWave Systems is bringing new technology developments to fruition through patents and technology licensing. In conjunction with its university research projects, AmberWave Systems conducts its own research, development and limited manufacturing in its semiconductor fabrication facility in Salem, New Hampshire. In addition, AmberWave Systems collaborates with other technology focused companies to further expand and develop its research. For more information about the company, please visit its Web site at www.amberwave.com.