Many questions, few answers, as IC vendors eye 'silicon plus'

David Lammers David Lammers
EE Times
(12/15/2003 2:31 PM EST)

WASHINGTON — Faced with a series of "impactful" choices that must be made over the next few months, technologists here at the 2003 International Electron Devices Meeting considered how to move past planar bulk CMOS to what is now being called "silicon plus"-the combination of strained silicon, silicon-on-insulator, high-k and multigate devices.

"The industry likes to make changes one step at a time, but there are too many things happening at once," said Mark Bohr, a senior fellow in charge of Intel Corp.'s process development group in Hillsboro, Ore. Intel and other silicon vendors face "very impactful decisions," Bohr added, that will affect corporate bottom lines for good or ill.

At IEDM, few companies said exactly what those decisions would be-either for the 65-nanometer node, moving to early manufacturing in about two years, or the 45-nm node, expected in late 2007.

The dozen papers on strained silicon presented over the three-day conference, the 49th IEDM, traveled two paths: "biaxial" or global strain, induced by depositing a graded silicon germanium layer across the entire wafer, and "uniaxial" strain, induced locally by process optimizations.

By introducing a compressive strain on its 90-nm PMOS transistors and a tensile strain on its NMOS devices, Intel took a uniaxial approach to become the first vendor to use strained silicon in production. For the PMOS devices, Intel used one additional mask layer to deposit SiGe only in the source and drain regions, adding compressive strain to the PFET channel. The strain stretches the atomic lattice of silicon by about 1 percent, improving carrier mobility. Intel claims its approach, requiring only one additional mask layer, gave the 90-nm PMOS devices a 25 percent boost for only a 2 percent cost adder overall.

Dmitri Antoniadis, a professor at the Massachusetts Institute of Technology who directs the multi-university Microelectronics Advanced Research Corp. (Marco) Center for Materials, Structures and Devices, called the local, uniaxial approach "strain lite."

"People have figured out how to control tensile stress just by carefully controlling what was already there, so in a sense it is nothing new," Antoniadis said, referring to the stresses in the silicon from the capping layer, the spacer, the shallow trench isolation and so on. Local strain "can get you a 5 to 10 percent net improvement on the NMOS drive current, and that is the easiest thing to do. After all, people do just what they need to do to meet their performance targets for a certain technology, at the least cost. That is what I would do if I were in industry. But I wouldn't call it a significant breakthrough."

IBM Corp. and Advanced Micro Devices Inc., which have partnered in developing their 65-nm and 45-nm processes, must decide in the next few months which road they will travel for their 65-nm silicon. Early indications are that the partners will use some form of locally strained silicon in combination with partially depleted silicon-on-insulator (SOI) at the 65-nm node. But the final decisions will be made in the first quarter, the companies said.

There is "no question that we are looking at local strain very seriously" for the 65-nm node and beyond, said Jeff Welser, director of next-generation technology components at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.).

Higher levels of strain can be achieved by using globally strained silicon, however, and that approach could result in the highest performance, said Welser, who co-authored one of the early papers on strained silicon while a graduate student at Stanford University in 1990.

Antoniadis of the Marco center said he believes the elimination of the SiGe buffer layer is the best approach, since thinner layers of silicon and buried oxide result in the fastest devices. IBM calls that approach strained silicon directly on insulator (SSDOI). By first depositing a graded SiGe layer and then removing that after a layer transfer approach, companies would end up with a thin strained-silicon layer, of 10 nm or so, on top of a thin buried oxide.

"Strained silicon across the entire wafer has the most appeal, but it is not devoid of problems, because it requires ultrathin films," Antoniadis said.

The major wafer manufacturers must be able to deliver strained silicon on SOI wafers at reasonable costs, with ultrathin layers of silicon and buried oxide. Toward that end, AmberWave Systems Inc. (Nashua, N.H.), a provider of strained-silicon intellectual property, last week announced a strategic relationship with Sumitomo Mitsubishi Silicon Corp., one of Japan's largest wafer manufacturers.

Carlos Mazure, chief technical officer at specialty-wafer supplier Soitec Inc. (Grenoble, France), said prototypes with 20 nm of strained silicon on top of a buried oxide layer have been developed in Soitec's lab using the company's layer transfer approach, called SmartCut. Through CMOS processing steps, the top silicon layer could be reduced much further, perhaps below 10 nm, he said.

At IEDM, IBM researcher Victor Chang discussed IBM's version of local strained silicon, which adjusts the isolation region and employs other process changes to induce strain. IBM could introduce that in a revised edition of its 90-nm technology.

Beyond 90 nm, Welser said, IBM could combine local strain with a thin SiGe buffer layer on top of a thin, partially depleted SOI layer. At the 45-nm node or beyond, IBM could make the layers even thinner by removing the SiGe buffer layer through a layer transfer approach, yielding strained silicon directly on oxide. Last week, IBM researcher Ken Rim presented an SSDOI approach that he claimed removes any serious threading defects, or misfits, that develop as the top silicon layer is strained. The approach delivers ultrathin layers: as little as 8 or 9 nm of strained silicon on top of 150 nm of buried oxide.

Thin silicon is required to avoid short-channel effects, and the higher levels of strain possible with the approach are not lost during transfer to the buried oxide layer, Rim said.

Whether IBM will use SSDOI in manufacturing remains an open question. One school of thought argues that as devices shrink and the channel length becomes smaller, the strains induced from less-intrusive local strain techniques become even more effective. Compressive strain from the source and drain regions becomes higher as the distance from the source and drain shrinks below 50 nm, for example.

As devices shrink, it will become too difficult to control yields with local strained silicon, said Gene Fitzgerald, a strained-silicon pioneer and MIT professor who is also chairman and founder of AmberWave, which licenses global strained-silicon technology to device and wafer manufacturers. "The real question with local strained silicon is whether companies can control parametric yields as they shrink," Fitzgerald said. "Will they be able to keep the same amount of strain, keeping their process parameters controlled for such local geometries?"

By contrast, Fitzgerald argued, global or wafer-scale straining introduces the same amount of strain for all devices. "You can still have process-induced strain on top of the global strain. The wafer-level approach is like a rising tide that lifts all boats: It increases drive current for all the transistors in a global shift."

Deciding on local, global or combined forms of strain is just part of the battle. Another crossroads comes at 45 nm: whether to introduce multigate devices with a relatively thick layer of silicon dioxide, as a means of controlling the channel and limiting leakage, or to stick with planar devices and introduce a high-k dielectric with metal gates.

"High-k could still be a win at the 45-nm node, but it is not in our critical path," said Ming Ren Lin, a fellow at AMD (Sunnyvale, Calif.). AMD's multigate devices, with gates on three sides of the channel, "can alleviate the need for high-k. We believe we are one step ahead of others in introducing SOI technology, and we could combine fully depleted SOI with our multigate approach and meet our on- and off-current targets without high-k."

But Meikei Ieong, a high-k development manager at IBM, said the shift to a multigate device would require major alterations to the design methodology, including circuit models, EDA layout tools and so on. While that might be more straightforward at companies that run high volumes of custom-design microprocessors, it would be a larger issue at companies that design a wider variety of products. And moving away from planar CMOS is an enormous technical transition, he noted.

Welser of IBM and Lin of AMD, in separate interviews, said the decisions facing the AMD-IBM alliance need to be finalized in the next three or four months, primarily on which form of strained silicon-local or global-to use for the 65-nm node, so that the companies can begin manufacturing in about two years.

For 45 nm, the choice between a high-k oxide with metal gates on planar devices or a fully depleted SOI multigate transistor with a metal gate, but without a high-k oxide, depends in part on progress in coming up with an acceptable high-k material that does not impact mobilities and control of the threshold voltages (see story, this page).

In early November, Intel announced it has chosen a form of high-k oxide that would be laid down with atomic-layer deposition technology. Because ALD is suited to hafnium oxide deposition and not to the forms of hafnium silicate planned for used at Texas Instruments, Toshiba and elsewhere, some experts believe Intel will move to a high-k oxide, such as hafnium oxide.

Bohr declined to say which high-k the company has selected. While Intel feels it has "gotten over the hump" with its high-k program, it still has a larger decision to make at the 45-nm node: whether to introduce its form of multigate transistor, called a trigate, or a planar transistor with a high-k oxide and metal gates. Further, Bohr said the trigate transistor could be built on bulk silicon wafers, with a few additional process steps, or with a fully depleted SOI technology that Intel calls depleted-substrate transistor.

"At this point I don't which is better. And a lot of people are wondering whether to introduce high-k or multigate transistors at the 45-nm node," Bohr said. "We wouldn't want to do both; that would be too many changes at once. A lot of serious discussion is going on right now."

About AmberWave Systems
Founded in 1998, AmberWave Systems has become a leader in the research, development and licensing of advanced technologies for semiconductor manufacturing. By funding and guiding university research, AmberWave Systems is bringing new technology developments to fruition through patents and technology licensing. In conjunction with its university research projects, AmberWave Systems conducts its own research, development and limited manufacturing in its semiconductor fabrication facility in Salem, New Hampshire. In addition, AmberWave Systems collaborates with other technology focused companies to further expand and develop its research. For more information about the company, please visit its Web site at www.amberwave.com.