What's Up From SEMI - Industry News
September 2002
The Decade of Materials starts with Silicon
Intel, IBM and several major Japanese semiconductor manufacturers view strained silicon as an enabling technology for <100 nm devices. Strained silicon technology leverages existing industry infrastructure, technology and tool sets, with relatively low additional cost compared to traditional processes. Possibly most important, strained silicon expands upon existing silicon wafer technology.
Introduction
It is next to impossible to be engaged in the semiconductor industry without encountering frequent references to Moore’s Law. In 1965, Gordon Moore, co-founder and Chairman Emeritus of Intel Corporation, made the observation that the number of transistors per integrated circuit (IC) were growing at an exponential rate and predicted that this trend would continue. Since that time, the industry has accomplished the exceptional feat of producing semiconductor devices with twice as many transistors as the prior generation every 18-24 months. Consumers and businesses alike have reaped tremendous benefits of essentially ubiquitous electronics technology, and semiconductors are at the heart of it all.
Over the past 30 years, the majority of the improvements in devices have been achieved via device scaling (also referred to as linewidth reduction) and materials innovations. Scaling involves shrinking all of the critical dimensions of the device (such as the gate or channel length and gate oxide thickness) by roughly the same factor. This in turn reduces the length of the path that electrons and holes have to travel, making the current in the devices flow faster and consume less power. However, scaling is becoming more challenging with each successive device generation, as fundamental technological limits of existing processes and materials are being reached. Even Gordon Moore himself has suggested that the progression of technology and performance improvements for semiconductor devices may slow down moving forward because of these technological barriers.
The Bottleneck
Currently, the most advanced generation of semiconductors employ geometries of 0.13 microns and have ~100 nm gates lengths with ~1.5 nm gate oxide thickness. Therefore, further reduction in gate length is limited. Atomic level interactions are inhibiting anticipated performance improvements from further scaling of devices. Many of these atomic level phenomena are demanding changes in the materials used in semiconductor processing, leading some to tag this as The Decade of Materials in the industry.
Given the restrictions associated with further reductions of the gate length in the quest to continue to increase device speed, the only alternative is to enhance the carrier (electrons and holes) mobility in the conducting channel. Mobility can be improved using a variety of new silicon technologies including strained silicon, silicon germanium, silicon on insulator (SOI), as well as combinations of these materials. Strained silicon is the focus of this discussion.
Strained Silicon
What is Strained Silicon?
Strained silicon refers to the interface of a silicon/silicon germanium hetero-structure. Silicon (Si) and germanium (Ge) atoms differ in size, with germanium being roughly 4% larger. Or, said another way, silicon and germanium have a lattice mismatch of ~4%, with lattice being a parameter used to define the unit cell size of an atom. It was discovered that the lattice mismatch between silicon and germanium atoms could be accommodated by a finite degree of lattice distortion. This distortion or strain actually offers the advantage of allowing electrons and holes to move more quickly (or have higher mobility). This increase in carrier mobility is attributed to a modified silicon band gap structure that lowers the resistance to electron and hole movement in the material. As a result, the use of strained silicon increases electron and hole mobility, and the resultant drive current or current flow, by 10-35%. Increased drive current means increased transistor speed. Further, a 30% speed gain can be translated into roughly two times lower power consumption.
Strained silicon is formed by the growth of a graded silicon germanium layer on top of a traditional silicon wafer. Then, another layer of silicon is grown on top of the silicon germanium layer, as shown in Figure 1. This final layer of silicon is strained at the silicon/silicon germanium interface. The larger crystalline lattice of silicon germanium exerts a strain on the thinner top silicon layers, stretching the silicon lattice slightly. Further, by controlling the amount of germanium in the silicon germanium layer, the amount of strain produced in the overlying silicon layer can be manipulated.
Figure 1 - Schematic of Strained Silicon Structure
Source: Leitz et al., Applied Physics Letters, 17 December 2001
The amount of germanium that is incorporated into the silicon germanium layer and the thickness of the overlying silicon layer determines the level of strain that is produced. Further, grading the silicon germanium layer with the right mix of germanium atoms is critical. An excessive concentration of germanium can create too much strain that leads to defects, while a silicon layer that is too thick can break under strain. It appears that germanium concentration of ~30-35% produces an optimum level of strain, delivering electron and hole mobility enhancements of 75-80%, which translate into drive current improvements of about half that level. This requires an overlying silicon film thickness of ~1000 Å. A thicker silicon layer can be grown and then thinned without relaxing the strain.
Strained Silicon Design and Process Integration Challenges
While there are significant benefits offered by strained silicon, there are also some process integration challenges that require further development. In general, strained silicon adds complexity to CMOS processing, as summarized in Figure 2. However, none of these challenges are considered to be show stoppers by the device community.
Figure 2 – Strained Silicon Design and Process Integration Challenges
Source: K. Rim, IBM
One of the major challenges with strained silicon is that while electron mobility in the n-FET (field effect transistor) is greatly improved in a strained silicon layer, a corresponding improvement in the hole mobility on the p-FET requires a much higher level of germanium in the graded silicon germanium layer. For reasons that are not well understood, hole mobility in the p-FET improves much less in strained silicon channels compared to dramatic gains in electron mobility in the n-FET. Further, PMOS devices, such as a p-FET, typically operate more slowly than NMOS devices, and this imbalance potentially worsens in strained silicon.
Additional challenges include maintaining the integrity of the strained silicon channel through subsequent processing at higher temperatures to prevent the relaxation of the strain. Further, the introduction of the silicon germanium layer creates additional interactions with materials that must be understood. Finally, silicon germanium has thermal characteristics that cause self-heating in the silicon and silicon germanium structures.
Commercialization of the Technology
Strained silicon technology has received significant attention from the semiconductor community in the past several years. Several major semiconductor companies have made announcements regarding the intention to implement this technology for <100 nm geometries, as summarized in Table 1. This is viewed as a true enabling technology, as it builds upon the infrastructure that exists in the semiconductor industry today and promises to offer improved speed ranging from 10-30% for a relatively small cost adder of 2-10%.
Table 1 – Selected Companies Involved in Strained Silicon
Source: Lubab Sheet, SEMI 2002
Company |
Strained Silicon
Announcement |
Implement Strained Silicon in Production |
Initial Strained Silicon Geometry |
Demonstrated Device Performance |
Initial Strained Silicon Device Type |
| AmberWave Systems Corp. |
2001 |
Not applicable |
Not available |
Electron and hole mobility enhancement factors of 1.5-2.2 |
Various (HBT, MOSFET, PMOSFET) |
IBM Microelectronics |
2001 |
2005 |
65 nm |
30% improvement in drain current |
Demonstrated NMOSFET with strained silicon channel |
Hitachi Ltd. |
2001 |
Not available |
<100 nm |
70% improvement for current drive in n-channel and 51% for p-channel |
MOS transistors with strained silicon channel |
| Intel Corp. |
2002 |
2H2003 |
90 nm |
10-20% increase in transistor current flow or drive current |
Demonstrated on 52 megabit SRAM chips to be used as a prototype in the production of Pentium 4 microprocessor “Prescott” |
Strained Silicon Materials Supply Considerations
As with any new materials technology in the semiconductor industry, consideration must be given to the reliable supply of material.
AmberWave Systems Corp, a licensor of strained silicon intellectual property (IP), and IQE Silicon, an epitaxial wafer service supplier, have reached an agreement in which IQE will supply 150 mm and 200 mm strained silicon wafers to AmberWave’s licensee customers. IQE has indicated that volume pricing of strained silicon wafers is anticipated to be approximately twice the price of prime wafers. The history of the semiconductor industry has proven that this type of price premium delays material adoption.
IBM Microelectronics has extensive expertise in SOI and silicon germanium and used ultra high vacuum chemical vapor deposition equipment to grow a graded silicon germanium buffer with a germanium content of 15-20%. It is unclear whether Intel developed its proprietary strained silicon process in house or in conjunction with a supplier.
However, when IBM initially adopted SOI it produced the material in house, but has since moved away from internal production to merchant sources. Unless the major wafer manufacturers begin to offer strained silicon wafers, including 300 mm, to the industry at an acceptable price premium, semiconductor manufacturers may have no alternative but to produce strained silicon in house.
-- Lubab L. Sheet is a Senior Market Analyst at Semiconductor Equipment and Materials International (SEMI) in San Jose, CA. Please feel free to contact her at lsheet@semi.org or (408) 943-6921 if you have questions or comments.
Special thanks to Craig Addison, Craig Klootwyk and Dan Tracy for their review and inputs!
About AmberWave Systems
Founded in 1998, AmberWave Systems has become a leader in the research, development and licensing of advanced technologies for semiconductor manufacturing. By funding and guiding university research, AmberWave Systems is bringing new technology developments to fruition through patents and technology licensing. In conjunction with its university research projects, AmberWave Systems conducts its own research, development and limited manufacturing in its semiconductor fabrication facility in Salem, New Hampshire. In addition, AmberWave Systems collaborates with other technology focused companies to further expand and develop its research. For more information about the company, please visit its Web site at www.amberwave.com.
|
