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J.-S. Park, J. Bai, M. Curtin, M. Carroll, and A. Lochtefeld, "Facet
Formation and Lateral Overgrowth of Selective Ge Epitaxy on
SiO-patterned Si(001) Substrates," J. Vac. Sci. Technol. B 26(1),
(Jan/Feb 2008). Read Article >
J. G. Fiorenza, J.-S. Park, and A. Lochtefeld, "Detailed Simulation
Study of a Reverse Embeded-SiGe Strained-Silicon MOSFET," IEEE Trans.
Electron Devices, 55, 640 (2008).
Read Article

J. Bai, J.-S. Park, Z. Cheng, M. Curtin, B. Adekore, M. Carroll, and A. Lochtefeld, M. Dudley, “Study of the defect elimination mechanisms in aspect ratio trapping Ge growth,” Appl. Phys. Lett., 90, 101902 (2007).
J.Z. Li, J. Bai, J.-S. Park, B. Adekore, K. Fox, M. Carroll, A. Lochtefeld, Z. Shellengarger, “Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping,” Appl. Phys. Lett., 91, 021114 (2007).
J.-S. Park, J. Bai, M. Curtin, B. Adekore, Z. Cheng, M. Carroll, M. Dudley, A. Lochtefeld, “Defect reduction and its mechanism of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping,” Mat. Res. Soc. Symp. Proc., 994, (2007). Read Article >
J.-S. Park, M. Curtin, C. Major, S. Bengtson, M. Carroll, A. Lochtefeld, “Reduced-pressure chemical vapor deposition of epitaxial Ge films on Si(001) substrates using GeCl4,” Electrochemical and Solid-State Letters, 10 (11), H313-H316 (2007). Read Article >
J.-S. Park, M. Curtin, J. Bai, S. Bengtson, M. Carroll, A. Lochtefeld, “Thin Strained Layers Inserted in Compositionally Graded SiGe Buffers and their Effects on Strain Relaxation and Dislocation,” J. Appl. Phys., 101, 053501 (2007). Read Article >
Y.Q. Wu, Y. Xuan, T. Shen, and P.D. Yea, Z. Cheng and A. Lochtefeld, “Enhancement-mode InP n-channel metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Al2O3 dielectrics,” Appl. Phys. Lett., 91, 022108 (2007). Read Article >
Y.Q. Wu, Y. Xuan, P.D. Yea, Z. Cheng and A. Lochtefeld, “Inversion-type enhancement-mode InP MOSFETs with ALD AL203, Hf02 and HfAlO nanolaminates as high-k gate dielectrics.”65th Device Research Conference (2007). Read Article >
J.S. Park et al., “Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using aspect ratio trapping,” Appl. Phys. Lett., 90, 052113 (2007).Read Article >
J. Huang et al., “A Study of compressively strained Si0.5Ge0.5 metal-oxide-semiconductor capacitors with chemical vapor deposition HfAlO as gate dielectric,” Appl. Phys. Lett., 90, 023502 (2007).

A. Lochtefeld, “Supercritical Strained Silicon on Insulator,” Mat. Sci. Eng. B, 135, pg. 228 (2006).
J.S. Park et al., “Growth of Ge Thick Layers on Si(001) Substrates Using Reduced Pressure Chemical Vapor Deposition,” Jap. J. Appl. Phys. 45.11, 8581 (2006). Read Article >
S. J. Kang et al., “Strain Degradation in Strained-Si Layers Far Thicker than the Critical Thickness Grown on Relaxed Si0.65Ge0.35 Layers,” ECS Transactions, 3.7, pg. 411 (2006).
K. Yao et al., “Strained Silicon Two-dimensional Electron Gases On Commercially Available Si1-xGex Relaxed Graded Buffers,” ECS Transactions, 3 .7, pg. 313 (2006).
M. Erdtmann et al., “Optimization of SiGe graded buffer defectivity and throughput by means of high growth temperature and pre-threaded substrates,” Mat. Res. Soc. Symp. Proc., 891, pg. 573 (2006).
C. Leitz et al., “Direct Regrowth of Thin Strained Silicon Films on Planarized Relaxed Silicon-Germanium Virtual Substrates,” Thin Solid Films, 513.1-2, pg. 300-306 (2006).
C. J. Vineis et al., “Optimized measurement of strained Si thickness and SiGe virtual substrate composition by spectroscopic ellipsometry,” Thin Solid Films, 513, pg. 78 (2006).
J. G. Fiorenza et al., “Systematic study of thick strained silicon NMOSFETs for digital applications,” Proceedings of the Third International SiGe Technology and Device Meeting, pg. 150 (2006).
J. Huang et al., “Surface NH3 anneal on strained Si0.5Ge0.5 for metal-oxide-semiconductor applications with HfO2 as gate dielectric,” Appl. Phys. Lett., 88.14, 143506 (2006).
M. Erdtmann et al., “The Crystallographic Properties of Strained Silicon Measured by X-Ray Diffraction,” J. of Mat. Sci.: Materials in Electronics, 17.2, pg. 137-147 (2006).
D. R. Black et al., “Imaging defects in strained-silicon thin films by glancing-incidence x-ray topography,” Appl. Phys. Lett., 88.22, 224102 (2006).
D. Isaacson et al., “Strained-Silicon on Silicon and Strained-Silicon on Silicon-Germanium on Silicon by Relaxed Buffer Bonding,” Journal of The Electrochemical Society, 153,.2, pg. G134-140 (2006).

I. Aberg et al., “Transport and leakage in super-critical thickness strained silicon directly on insulator MOSFETs with strained Si thickness up to 135 nm,” Technical Digest of the 31st IEEE International SOI Conference, pg. 24-26 (2005).
M. L. Lee, et al., “Strained Si, SiGe, and Ge Channels for High-Mobility Metal-Oxide-Semiconductor Field-Effect Transistors,” J. Appl. Phys., 97, 011101 (2005).
C. Leitz et al., “A high throughput, ultra-low roughness, SiGe-free strained Si regrowth process,” Mat. Sci. in Semi. Process, 8, pg. 187 (2005).

C. L. Chen, et al., “DC and RF Characterization of Fully-Depleted Strained SOI MOSFETs,” Technical Digest of the 30th IEEE International SOI Conference, pg. 86-88 (2004).
J. Bennett, et al., “SIMS Depth Profiling of B and As Implants in Si1-xGex and Strained Si/Si1-xGex,” Proceedings of the First International Symposium on SiGe: Materials, Processing, and Devices, pg. 239-241 (2004).
P. Kohli, et al., “Ultra-Shallow Junction Formation in Strained Si/Si1-xGex using Flash-Assist RTA,” Proceedings of the First International Symposium on SiGe: Materials, Processing, and Devices, pg. 1113-1114 (2004).
R. Westhoff, et al., “A Novel High Quality SiGe Graded Buffer Growth Process Using GeCl4,” Proceedings of the First International Symposium on SiGe: Materials, Processing, and Devices, pg. 589 (2004).
M. T. Bulsara, “SiGe Graded Layer Technology Ready to be Incorporated into III-V Optical Interconnect Systems,” MRS Bulletin, 29. 9, pg. 611-12 (2004).
M. T. Bulsara, “Strained Silicon Substrate Technology: Commercialization Fundamentals,” Yield Management Solutions, 6. 2, pg. 35 (2004).
M. T. Bulsara, “Optical Interconnects Promised by III-V On-Silicon Integration,” Solid State Technology, Aug. 2004, pg. 22 (2004).
M. T. Bulsara, “Recent Developments in Strained Silicon-Based Substrate Fabrication,” SEMI Technology Symposium: Innovations in Semiconductor Manufacturing, Jul. 2004, pg. 151 (2004).
L. K. Bera, et al., “Investigation of Electrical Properties of Furnace Grown Gate Oxide on Strained-Si,” Thin Solid Films, 462-463, pg. 85-89 (2004).
M. T. Currie (invited), “Strained Silicon: Engineered Substrates and Device Integration,” Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology, pg. 261-268 (2004).
T. A. Langdo, et al., “Strained Silicon on Insulator Technology: From Materials to Devices, Solid-State Electronics,” 48. 8, pg. 1357-1367 (2004).
M. Erdtmann, et al., “X-ray Reflectivity of Strained Silicon on Insulator Substrates,” Proceedings of the Second International SiGe Technology and Device Meeting, pg. 238 (2004).
J. G. Fiorenza, et al., “Evaluation of Strained Silicon MOSFETs for RF and Analog Circuit Applications,” Proceedings of the Second International SiGe Technology and Device Meeting, pg. 137-138 (2004).
C. Leitz, et al., “A High-Throughput, Ultra-Low Surface Roughness, SiGe-Free Strained Si Regrowth Process,” Proceedings of the Second International SiGe Technology and Device Meeting, pg. 113 (2004).
J. G. Fiorenza, et al., “Investigation of Misfit Dislocation Leakage in Supercritical Strained Silicon MOSFETs,” Proceedings of the 2004 IEEE International Reliability Physics Symposium, pg. 493-497 (2004).
L. K. Bera, et al., “Analysis of Carrier Generation Lifetime in Strained-Si/SiGe Heterojunction MOSFETs from Capacitance Transient,” Appl. Surf. Sci., 224.1-4, pg. 278-282 (2004).
I. Lauer, et al., “Fully-Depleted n-MOSFETs on Supercritical Thickness Strained Silicon on Insulator,” IEEE Electron Dev. Lett., 25. 2, pg. 83-85 (2004).
M. T. Bulsara, “Strained Silicon: From Research to Adoption,” Elec. J. (Japan), Feb. 2004, pg. 64 (2004).
J.G. Fiorenza, et al., “Film Thickness Constraints for Manufacturable Strained Silicon CMOS,” Semicond. Sci. Technol., 19, pg. L4 (2004).

M. Erdtmann, et al., “Growth and Characterization of High-Ge Content SiGe Virtual Substrates,” Proceedings of 204th Meeting of Electrochemical Society (2003).
T.A. Langdo, et al., “Advanced SiGe-Free Strained Si on Insulator Substrates: Thermal Stability and Carrier Mobility Enhancement,” SSDM, pg. 814 (2003).
M. Erdtmann, et al., “Structural Characterization of Strained Silicon Substrates by X-Ray Diffraction and Reflectivity,” SSDM, pg. 290 (2003).
M.T. Bulsara, “Commercial Advances in Strained Silicon Technology,” SEMI Technology Symposium: Innovations in Semiconductor Manufacturing, pg. 237 (2003).
T.A. Langdo, et al., “SiGe-Free Strained Si on Insulator by Wafer Bonding and Layer Transfer,” Appl. Phys. Lett., 82, pg. 4256 (2003).
J.R. Hwang, et al., “Performance of 70 nm Strained-Silicon CMOS Devices,” Symp. on VLSI Tech., pg.103 (2003).
J.-S. Goo, et al., “Scalability of Strained-Si nMOSFETs Down to 25 nm Gate Length,” IEEE Elec. Dev. Lett., 24, pg. 351 (2003).
V. Higgs, et al., “Dislocation Detection in Strained Si Using Photoluminescence Mapping,” Proceedings of 3rd International Conference on SiGe(C) Epitaxy and Heterostructures, pg. 270 (2003).
Q. Xiang, et al., “25 nm Gate Length Strained Silicon CMOS,” First International SiGe Technology and Device Meeting, pg. 13 (2003).

T. A. Langdo, et al., “Preparation of Novel SiGe-Free Strained Silicon on Insulator Substrates,” 2002 IEEE International SOI Conference, pg. 211 (2002).
E.A. Fitzgerald, et al., “MOSFET Channel Engineering Using Strained Si, SiGe, and Ge Channels,” SSDM, pg. 145 (2002). |